1. Field of the Invention
This invention relates to improvements in a phase-locked loop circuit (hereinafter referred to as a PLL circuit) for obtaining output oscillations in phase with an incoming signal.
2. Description of the Prior Art
Analog and digital PLL circuits are often used in various types of apparatus. However, these conventional PLL circuits have not been suited for some applications requiring high speed response and a high degree of stability.
FIG. 1 of the accompanying drawings is a block diagram showing the conventional PLL circuit. The circuit includes a phase detector 1 (hereinafter referred to as PD); a low pass filter 2 (hereinafter referred to as LPF) serving as a loop filter for the PLL circuit; a voltage controlled oscillator 3 (hereinafter referred to as VCO); an 1/n frequency divider 4; and an input terminal 5 to which an incoming signal is supplied. The phase detector 1 can generally be classified as either an analog type or a digital type. The PLL circuit is also classified either as an analog or digital type, depending on the type of phase detector used.
FIG. 2 shows by way of example the arrangement of the essential parts of the conventional analog type PLL circuit. FIG. 2 includes a wave-form shaping circuit 6 and a multiplier circuit 7 which jointly form a phase detector such as the phase detector (PD) 1 shown in FIG. 1. An LPF 2a corresponds to the LPF 2 of FIG. 1. A terminal 8 receives a phase detecting square wave produced from the 1/n frequency divider 4 of FIG. 1 for phase detection. A terminal 9 corresponds to the terminal 5 of FIG. 1 and receives a square wave signal (such as the horizontal synchronizing signal of a television signal) as an external incoming signal in the form of pulses of a narrow width not exceeding a duty cycle of 50%. A terminal 10 supplies an output signal to the VCO 3 of FIG. 1. Another terminal Vcc is arranged to have a power supply voltage impressed thereon. A terminal VB is arranged to have a bias voltage impressed thereon.
FIG. 3 is a timing chart showing the wave forms of the various parts (a)-(e) shown in FIG. 2. In operation, the phase detecting square wave (a) produced from the 1/n frequency divider 4 is converted into a saw tooth wave (b) by the wave-form shaping circuit 6 composed of an RC passive element. The saw tooth wave (b) is supplied to the multiplier 7. The external incoming square wave signal (c) is supplied to the input terminal 9. At the multiplier 7, a part of the saw tooth wave (b) is extracted by the incoming external square wave signal (c) through a multiplying operation, as shown at (d) in FIG. 3.
An LPF 2a which serves as a loop filter and is composed of a resistor R and capacitor C is arranged to pass only a low frequency component of the extracted signal (d). The low frequency component corresponds to a phase difference between the incoming external signal (c) and the phase detecting square wave (a). The signal (d) is then controlled by a control signal (e) to increase the oscillation frequency of the VCO 3 when the oscillation phase of the VCO 3 is delayed and to decrease it when the phase is ahead of the correct phase. The VCO 3 is thus controlled to decrease the phase error until a phase locked state is obtained.
In the analog PLL circuit arranged as described above, the VCO is controlled throughout the whole period of operation. However, since the detection of phase deviation is carried out in a predetermined cycle, a certain length of time is required before information on phase deviation is reflected in control over the VCO. This results from the fact that the response speed of the whole PLL circuit is determined by that of the LPF 2a. The responsivity of the LPF 2a thus makes it difficult to obtain a high speed responsive PLL circuit. Assuming that the frequency of the incoming external square wave signal is 15.374 KHz (the horizontal synchronizing frequency of a television signal), the LPF 2a must adequately remove the 15.734 KHz component and the components related thereto from the output of the multiplier 7. To meet this requirement, the cut-off frequency of the LPF 2a in general must be set at several hundred Hz. This requirement has prevented the LPF 2a from having a quick response.
In an analog PLL circuit of this type, it is conceivable to attenuate the frequency component of the incoming external square wave signal by sample-and-holding the output of the multiplier 7. Even in that event, however, an LPF is indispensable. Besides, assuming that the frequency of the incoming external square wave signal is fr, the sample-and-holding operation results in a wasted time of 1/fr sec (63.556.mu. sec where fr=15.734 KHz). This causes some degradation of the frequency characteristic. Therefore, no substantial improvement can be expected from such an arrangement. Further, the stability of the PLL circuit is impaired by a phase delay resulting from the operations of an LPF and a sample-and-holding arrangement.
FIG. 4 shows by way of example the arrangement of the conventional digital PLL circuit. In FIG. 4, the same component elements as those shown in FIG. 1 are indicated by the same reference numerals and symbols. An AND gate 11 and an LPF 2b correspond, respectively, to the PD and to the LPF of FIG. 1. FIGS. 5(A), 5(B), and 5(C) are timing charts of the wave forms of the various parts (a)-(d) shown in FIG. 4.
FIG. 5(A) shows the PLL circuit of FIG. 4 in a phase locked state. FIG. 5(B) shows it in a state wherein the output (b) of the frequency divider 4 has for some reason gained in phase and ends up ahead of the incoming external square wave signal (a). As apparent from the drawing, when the phase of the signal produced from the frequency divider 4 gains, that is, when the phase of the oscillation signal of the VCO 3 gains, the pulse width of the pulses (c) produced from the AND gate 11 become narrower than the width obtained at the time of phase lock. The control voltage (d) supplied to the VCO 3 thus decreases. Accordingly, the oscillation frequency of the VCO 3 decreases and the phase of the oscillation signal from the VCO 3 is delayed. As a result, the PLL circuit is pulled into a phae-:locked state as shown in FIG. 5(A). FIG. 5(C) shows a state wherein the phase of the signal produced from the frequency divider 4 is lagging behind that of the incoming external square wave signal (a). Again, as apparent from the drawing, the pulse width of the pulses (c) produced from the AND gate 11 becomes wider than the width obtained at the time of phase lock and the control voltage supplied to the VCO 3 increases. The oscillation frequency of the VCO 3, therefore, also increases and advances the phase of the oscillation signal of the VCO 3. The PLL circuit is thus pulled into a phase locked state.
In the digital PLL circuit described above, the VCO is controlled throughout the entire period of operation. The conventional digital PLL circuit thus necessitates the use of some smoothing element such as an LPF. Therefore, the digital PLL circuit also brings about some response delay in the same manner as in the analog type PLL circuit previously described. It has thus been extremely difficult to obtain a quick response PLL circuit. Moreover, the stability of the operation of the conventional PLL circuit is impaired by the response delay.